1. Field of the Invention
The present invention relates generally to synchronous semiconductor memory devices synchronized with a clock signal and particularly to configurations of output buffer circuits.
2. Description of the Background Art
In microfabrication of a transistor, scaling a device down is not always associated with accordingly scaling a power supply voltage down, and the power supply voltage can be maintained constant while the device""s dimension can be reduced. In this case, the transistor provides an intense electric field in a vicinity of the drain. Hot carriers are thus produced in a channel and jump into a gate oxide film to impair the transistor""s device characteristics disadvantageously. One approach to solve this problem is xe2x80x9cNormally-On Enhancement MOSFET Insertion (NOEMI).xe2x80x9d
FIG. 15 shows one example of an NOEMI output buffer circuit internal to an LSI.
With reference to FIG. 15, this NOEMI output buffer circuit operates in response to data signals TO, /OT to transmit data to an output terminal OP connected to an external bus. Data signals OT, /OT are complementary signals corresponding to data output from the LSI externally. Data signal/OT corresponds to an inverted version of data signal OT. Hereinafter similarly the mark xe2x80x9c/xe2x80x9d used with a signal will indicate an inverted version of the signal. For example, a signal /S is an inverted version of a signal S.
This output buffer circuit is provided with an n channel MOS transistor NT2 connected between an output node NO of an inverter formed by a n channel MOS transistor NT1 and a p channel MOS transistor PT1 and a drain terminal of transistor NT1. Transistor NT2 has its gate constantly receiving a power supply voltage VCC. Transistor NT2 is thus constantly turned on. By the provision of transistor NT2 the transistor NT1 drain voltage is limited to a voltage Vd=Vgxe2x88x92Vth, wherein voltage Vg to a gate voltage of transistor NT2 and voltage Vth corresponds to a threshold voltage Vth of transistor NT2.
The insertion of transistor NT2 can thus limit a drain voltage applied to transistor NT1 and thus prevent the transistor from having poor device characteristics attributed to injection of hot carriers.
FIG. 16 shows a configuration of a non-NOEMI output buffer circuit.
The FIG. 16 circuit is identical in configuration to the FIG. 15 circuit minus transistor NT2. It transmits to node NO the data corresponding to complimentary data signals OT, /OT.
FIG. 17 conceptually represents a region of a capacitance corresponding to a load (hereinafter also referred to as a xe2x80x9cload capacitancexe2x80x9d) of output node NO for the non-NOEMI output buffer circuit of FIG. 16.
With reference to FIG. 17, transistors PT1 and NT1 are shown to form an output buffer circuit formed on a substrate. In a region shown in FIG. 17 in which transistor PT1 is formed the source""s side is connected to power supply voltage VCC and the drain""s side is connected to node NT0. The gate receives the level in voltage of data signal /OT input. In a region in which transistor NT1 is formed the source""s side is connected to a ground voltage GND and the drain""s side is connected to node N0. The gate receives the level in voltage of data signal OT input. For this non-NOEMI output buffer circuit, output node NO is associated with a load capacitance corresponding to a region on the side of the drain of transistor PT1 (a drain junction capacitance on the side of transistor PT1) and a region on the side of the drain of transistor NT1 (a drain junction capacitance on the side of transistor NT1). More specifically, as shown in FIG. 17, a hatched region on the side of the drains of transistors PT1 and NT1 corresponds to a region of a load capacitance imposed on output node N0.
FIG. 18 conceptually represents a region of a load capacitance of output node N0 for NOEMI output buffer circuit of FIG. 15 with transistor NT2 constantly turned on.
With reference to FIG. 18, transistors PT1, NT1 and NT2 are shown to form an NOEMI output buffer circuit formed on a substrate. As has been described previously, FIG. 18 is different from FIG. 17 in that transistor NT2 is further provided on a substrate at a predetermined region in which an N-type transistor is formed.
Transistor NT2 is provided between transistor NT1 and node N0 and the transistor NT1 drain""s side and the transistor NT2 source""s side are electrically coupled together. Transistor NT2 has its gate receiving power supply voltage VCC and the transistor NT2 drain""s side is connected to node N0.
Node N0 has a load capacitance imposed thereon, as follows: with its gate constantly receiving power supply voltage VCC, transistor NT2 is constantly turned on and the capacitance of the gate of transistor NT2 and that in a region closer to the drain of transistor NT1 or the source of transistor NT2 (an inter-gate junction capacitance) are added to node N0 in addition to a drain junction capacitance of transistors PT1 and NT2. Thus while the NOEMI output buffer circuit with transistor NT2 constantly turned on can prevent injection of hot carriers it would disadvantageously introduce increased load capacitance.
This increased load capacitance is never negligible for memory systems having a high speed interface such as synchronous dynamic random access memory (SDRAM), double data rate (DDR) SDRAM and the like.
FIG. 19 shows a concept for implementing rapid data transfer in a memory system having a high speed interface. As shown in FIG. 19, LSIs each have output terminal OP electrically connected to an output node of an output buffer circuit and are connected in parallel to an external bus.
FIG. 20 compares data waveforms based on a difference between a load capacitance of output node N0 of a non-NOEMI output buffer circuit and that of the node of an NOEMI output buffer circuit when data is transferred rapidly.
If the LSI is configured with the non-NOEMI output buffer circuit a small load capacitance is imposed on output terminal OP. Thus, as shown in FIG. 20, if data is transferred rapidly, with the small load capacitance imposed on output terminal OP, the data can be transmitted in a short period of time with a desired level. If the LSI has the NOEMI output buffer circuit then a load capacitance larger than for the non-NOEMI output buffer circuit is imposed on output terminal OP. As such, if data is rapidly transferred, with a large load capacitance imposed on output terminal OP, the data is hardly transmitted in a short period of time with a desired level. As a result, data transferred would provide a signal level lower than before the data is rapidly transferred. This can result in a detection portion internal to a system erroneously recognizing the transferred data.
The present invention contemplates a synchronous semiconductor memory device capable of rapid data transfer, having an NOEMI output buffer circuit with an output terminal free from significant load capacitance.
The present invention in one aspect provides a synchronous semiconductor memory device operating in synchronization with a clock signal, including a memory array, a control signal generation circuit, an output buffer circuit, and an output control circuit. The memory array has a plurality of memory cells arranged in rows and columns and each storing data. The control signal generation circuit receives an external instruction input in synchronization with the clock signal to generate a control signal for defining a data output period in response to the external instruction. The output buffer receives data read from the memory array for output to an output node during the data output period. Furthermore the output buffer circuit includes a first transistor connected between the output node and a first voltage, a second transistor connected between the output node and a second voltage, and a third transistor connected between the output node and the second voltage in series with the second transistor. The output control circuit controls turning on/off the first, second and third transistors and in the data output period complementarily turns on and off one of the first and second transistors in response to the read data and also turns on the third transistor in response to the control signal.
A main disadvantage of the present synchronous semiconductor memory device is that the third transistor can be turned on only for a data output period to reduce a load capacitance imposed on an output node when a data output operation starts. If data is rapidly transferred, a time required to charge/discharge the output node in accordance with data to be transferred can be reduced to sufficiently ensure a level of a signal of data to allow steady data transfer.
The present invention in another aspect provides a synchronous semiconductor memory device operating on one of a first voltage and a second voltage higher than the first voltage in synchronization with a clock signal, including a memory array, a control signal generation circuit, an output buffer circuit, and an output control circuit. The memory array has a plurality of memory cells arranged in rows and columns and each storing data. The control signal generation circuit receives an external instruction input in synchronization with the clock signal to generate a control signal for defining a data output period in response to the external instruction. The output buffer receives data read from the memory array for output to an output node during the data output period. Furthermore the output buffer circuit includes a first transistor connected between the output node and a first power supply node, a second transistor connected between the output node and a second power supply node, and a third transistor connected between the output node and the second power supply node in series with the second transistor. The output control circuit controls turning on/off the first, second and third transistors. When the first power supply node is connected to the second voltage and the second power supply node is also connected to a third voltage lower than the first and second voltages, the output control circuit in the data output period complementarily turns on and off one of the first and second transistors in response to the read data and also turns on the third transistor in response to the control signal. When the first power supply node is connected to the first voltage and the second power supply node is also connected to the third voltage, the output control circuit in the data output period complementarily turns on and off one of the first transistor and one of the second and third transistors in response to the read data.
The present synchronous semiconductor memory device can change a signal input to the gate of the third transistor between its operation on the first voltage and that on the second voltage higher than the first voltage. As such, when the first, low operating voltage is used, without the output node having a high voltage applied thereto, the output buffer circuit can be configured to be of non-NOEMI, and when the second, high operating voltage is used, with the output node having a high voltage applied thereto, the output buffer circuit can be configured to be of NOEMI so as to generalize a design of an output buffer among devices operating on different levels of voltage.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.